MS patent #5628686
defines them as:
When the INT0 input 134 returns to a high logic level, a second analog mode interrupt request 352 must be generated within a predetermined period of time t.sub.1, as shown in FIG. 9. In the presently preferred embodiment, the second analog mode interrupt request 352 must occur between 115 .mu.sec and 305 .mu.sec of the time at which the INT0 input 134 (see FIG. 3C) returned to a low logic level. If the second analog mode interrupt request 352 does not occur within this time frame, there is no valid Switch to Digital command and the second analog mode interrupt request is merely treated as another request for position data. If the second analog mode interrupt request 352 does occur within the required time frame, the microprocessor 124 records the precise time t.sub.1 and stores the time, designated as t.sub.v. When the INT0 input 134 returns to a high logic level, a third analog mode interrupt request 354 must be generated with a predetermined period of time t.sub.2. When the INT0 input 134 returns to a high logic level, a fourth analog mode interrupt request 356 must be generated within a predetermined period of time t.sub.3 as shown in FIG. 9. The time periods t.sub.1, t.sub.2 and t.sub.3 are all different time periods to prevent the accidental transition of the digital joystick 102 from the Analog Emulation Mode 302 to the Digital Transmission Mode 300 by computer software programs. As stated above, the time period t.sub.1 is designated as t.sub.V only if it is greater than 115 .mu.sec and less than 305 .mu.sec. The time periods t.sub.2 and t.sub.3 must satisfy the equations below:
such that all three time periods t.sub.1, t.sub.2, and t.sub.3 must be within specified ranges. If the four analog mode interrupt requests 350, 352, 354, and 356 do have the specified timing relationship, the digital joystick 102 switches from the Analog Emulation Mode 302 (see FIG. 4) to the Digital Transmission Mode 300. Thus, the system 100 can effectively send commands to the digital joystick 102 in either the Digital Transmission Mode 300 or the Analog Emulation Mode 302 (see FIG. 4).
100us as t1 is too tight, maybe that's the problem.
I use t1=140us, t2=140+725us, t3=140+300us.
Edit: heh, was skimming again. Obviousely you read the patent
In general using the lower bound values is prefered since it gives you leeway to compensate for \"slow\" gameports. 100us + charge until INT0 is asserted on a \"fast\" gameport is probably > 115us. Not sure how fast build-in gameports from a couple years ago are tho, may be too fast to reach the 115us.